There is a need in new portable and low-power computing systems to save power wherever possible, with minimal sacrifice of system response-time and performance. One common method of power-saving is to stop the system clocks, and further, to stop any associated clock oscillators, because clocks and oscillators, and circuits driven by them, consume considerable power. System clocks and associated clock oscillators are used primarily to establish time bases by which logical processes within digital circuits are carried out. For systems which require high-accuracy clock frequencies, crystal oscillators or high-Q ceramic resonators are used to generate precise system clocks.
Crystal oscillator and ceramic resonator devices have several issues involved with their use. First, the oscillation may not be reliable or stable during clock-generator startup, either during a power-on reset (POR), or restarting of oscillation when exiting reduced power "sleep mode". Second, the power-efficiency may not be as good as with other clock generation methods. Third, if the system clocks are to remain off during clock-generator startup, there needs to be a method to detect when the clock startup sequence or procedure is complete. One method would be to impose a time delay upon other processing until the clock has stabilized, the delay being of sufficient duration to ensure clock stability; however, measurement of the delay is problematic in the sense that the most readily available time base for measuring such a delay is the clock generator itself, and it will not be stabilized or otherwise available during its initial startup interval.
Alternative techniques, such as resistor-capacitor (RC) discharge techniques, are coarse, and they require an external resistor-capacitor network and connection pin of an application specific integrated circuit (ASIC). In addition, it should be noted that POR delay circuits may not be applicable to oscillator startup when exiting from a sleep mode, since a system or ASIC full reset may not be desired; and, unlike cycling of the system power supply which does produce sufficient delay, the signal which ends sleep-mode may not be of sufficient duration to discharge a simple RC POR circuit.
Finally, startup time of system clock generators may be long enough to delay system response, hurt system performance, and unnecessarily waste power while the system is waiting for the clock generator to stabilize.
A second clock generator could be used to address the issues surrounding crystal oscillators and ceramic resonator devices, but it is desirable that the second clock generator would add little or virtually no cost to the system, and would consume little or no space within the system, e.g. on a printed circuit board. There are many tasks which can be handled while the primary clock source is shut down or starting up, which do not require the full accuracy of the primary clock source. Temporary or intermittent operation of the second clock generator may be crucial in systems where processing tasks cannot wait until the primary clock source has started-up and stabilized. Also, desirably, the second clock source should impose shorter startup times and greater oscillation power efficiency, resulting in further power savings. A hitherto unsolved need has remained for a secondary clock generator which satisfies these desirable requirements.